The road traveled in this project was much longer than I had envisioned when I first started out, thinking this was going to be an easy and quick turn around. But as they say, all good things require time and hard work in order to accomplish, and that has certainly been the case here as well. We lost a few members of the Beta Team along the way. One because of my mishandling of what was expected, and the other because of personal issues. The drop-in FujiNet adapter board is still in the works, but I think that will get sorted out before the public release of this project. So all in all I think things have been going quite well.
And now for a look at the first assembled board straight out of the sample batch. Pretty much a 99.99% perfect fit for all of the components. Only had to leave out one By-Pass IC decoupling capacitor (lower right corner) which had a lead soldered too darn close to one of the SMT chips on the bottom side. Because of the lack of space to put it elsewhere, it will be removed from the design all together. Since the board has a good distribution of these capacitors, and being a 4-layer board with inner power planes, the loss of one decoupling capacitor is not seen as an issue.
The schematic has been updated to reflect any last minute changes in the sample boards, and the resulting pdf has been provided for download.
The production boards will be identical to what you see above, albeit missing the by-pass capacitor that had clearance issues. The version number will stay the same, since the sample boards will remain with the beta test group members, and the change is relatively minor. Oh and that improper bottom side board ID label will get corrected as well
The Gerber files, BOM, and various flashing files for the PICs, PLDs, and OS ROM will all be released to the public in approximately 2-3 months. However a couple of people that are opting to build and sell these boards in a fully assembled and tested state will get a head start on this aspect.