;****************************************************************************
;*  Name    : C64_VGATE.asm 
;*  Author  : Michael St. Pierre
;*  Notice  : Copyright (c) 2024 Mytek Controls
;*          : All Rights Reserved
;*  Date    : 2/18/2024
;*  Version : 1.0 (Eliminate Left-Side Over Scan and White Line)
;*  Notes   : Over-Scan Timing Generator (V-Gate Chip)
;*          : Based on Microchip PIC12F1572
;*          : Assembled in GPUTILS 
;*          : Source: <https://gputils.sourceforge.io/>
;*
;*          : Firmware for C64 VGATE Over-Scan/White Line Eliminator
;*          : 
;* 
;*  This program is free software; you can redistribute it and/or modify
;*  it under the terms of the GNU General Public License as published by
;*  the Free Software Foundation, either version 2 of the License, or
;*  (at your option) any later version.*
;*
;*  This program is distributed in the hope that it will be useful,
;*  but WITHOUT ANY WARRANTY; without even the implied warranty of
;*  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
;*  GNU General Public License for more details.
;* 
;*  You should have received a copy of the GNU General Public License along
;*  with this program.  If not, see <http://www.gnu.org/licenses/>
;*
;****************************************************************************

    list p=12F1572	      ;Define Processor
    #include <p12f1572.inc>

; Set configuration register for:
; Code protection off
; Brown-out detect off
; MCLR disabled (I/O Pin)
; Watch Dog timer disabled
; Power on reset delay enabled
; Enable External Clock Input (8.18 Mhz NTSC VIC2 DOT CLK pin-22)
; 4x PLL enabled (32.72Mhz)

;PIC12F1571 Config Settings
    __CONFIG _CONFIG1, _FOSC_ECM & _WDTE_OFF & _PWRTE_ON & _MCLRE_OFF & _CP_OFF & _BOREN_OFF & _CLKOUTEN_OFF
    __CONFIG _CONFIG2, _WRT_OFF & _PLLEN_ON & _LVP_OFF 

;**********************************************************************
;Variables and Equates
;**********************************************************************             
    cblock 0x20

dlyloop

    endc

#DEFINE CE      PORTA,0       ; VGATE Enable/Disable 0 = OFF (default = ON) 
#DEFINE CSYNC   PORTA,2       ; Video Sync Input   
#DEFINE VGATE   PORTA,4       ; VGATE Video Switch
                              ; PORTA,5 Dot Clock Input

;**********************************************************************
;Start
;**********************************************************************

    org     0x000	      ; Processor reset vector
    goto    SetUp	      ; Set up Port I/O, IRQ, ect.

;----------------------------------------------------------------------
	
    org     0x004	      ; Processor interrupt vector


    movlw   16H               ; Wait 9.1 us (sync+color burst)
    call    dly_405ns
    

    bcf     VGATE	      ; Turn off video for 1.5 us (over-scan deleted)
    movlw   02H
    call    dly_405ns
    nop

   
    bsf     VGATE	      ; Turn on video (display active video data)


    banksel INTCON	      ; Clear interrupt flag
    bcf     INTCON,INTF
    retfie	              ; Leave interrupt


;**********************************************************************
;Setup
;**********************************************************************

SetUp	
	
; configure Ports

    banksel TRISA
    movlw   B'11101111'	      ; RA4 Output, all others input
    movwf   TRISA
    banksel WPUA		
    movwf   WPUA	      ; Enable individual pull-ups for PORTA inputs
    banksel ANSELA
    clrf    ANSELA	      ; Switch PORTA from analog to digital inputs
	
; configure interrupts
	
    banksel OPTION_REG
    bsf     OPTION_REG,INTEDG     ; 1 = interrupt on CSYNC rising edge
    bcf     OPTION_REG,7	  ; Global enable weak pull-ups

    banksel INTCON
    bsf     INTCON,INTE	      ; 1 = enables the GPIO port change interrupt
    goto    Main


;**********************************************************************
;Subroutines
;**********************************************************************

dly_405ns
    movwf   dlyloop
dly decfsz  dlyloop,1
    goto    dly
    retlw   0


;**********************************************************************
;Main Loop
;**********************************************************************

Main
    bsf     VGATE             ; Video ON
    btfsc   CE
    bsf     INTCON,GIE	      ; If CE=1 then enable all interrupts
    btfss   CE
    bcf     INTCON,GIE	      ; If CE=0 then disable all interrupts
    goto   Main               ; Loop while waiting for interrupt   
    end